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Chalcogenide Semiconductor Lab

People

Professor

Prof.  Daehwan Kang (Ph. D)

Dep. of Semiconductor Engineering, POSTECH

Emerging semiconductor device and process architecture
Development of 2T-0C DRAM device
Neuromorphic device application using Atomic Layer Deposited OTS materials

Professor

Prof.  Daehwan Kang (Ph. D)

Dep. of Semiconductor Engineering, POSTECH


Emerging semiconductor device and process architecture

Development of 2T-0C DRAM device

Neuromorphic device application using Atomic Layer Deposited OTS materials

77, Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea
daehwankang@postech.ac.kr
+82-54-279-7085

Careers & Experiences

  • Dep. of Semiconductor Engineering in Pohang University Science and Technology (POSTECH), Professor (2023.02~present) 
    • Development of 4D Stackable 2T-0C DRAM device based on ultrathin channel FET (23.5~27.12.31)2T-0C devices based on oxide semiconductor channel materials
    • Neuromorphic device application using Atomic Layer Deposited OTS materials (23.3.15~25.9.16)


  • Advanced Technology Team in National Institute for Nanomaterials Technology (NINT), Manager (2023.05~present) 
    • Development of 8-inch SiC Wafer-based Multi-Sensor SoC Platform (23.4~27.12)


  • Samsung Electronics Co., Ltd. Semiconductor R&D Center, Principal Researcher (2005. 12~2023.01) 
    • Development of 3D stackable PRAM (Phase-change Random Access Memory) with 19nm technology as a Project Leader who supervises a Technology Development (TD) department and characterization of tens of Gbit-level PRAM prototype device.
    • Development and production of 512Mb, 1Gb PRAM with 39/58/82nm technologies as a Part Leader who led and co-worked with a dozen of device engineers for improving cell performances and reliabilities of wafer-/package-level PRAM device.


  • Korea Institute of Science and Technology, Senior Researcher (2004. 2~2005.11) 
    • In-situ electrical evaluation of the threshold switching and crystallization processes of amorphous chalcogenide semiconductors


  • Research Institute of Advanced Materials, Seoul National University, Research Fellow (2002. 3~2004. 1)
    • Investigation on thermal and electrical characteristics of electrode materials for highly Joule heating in the phase change memory cell operation by a heat conduction simulation


  • SK Hynix Semiconductor, Inc., Memory R&D Division, Senior Researcher (1997. 9~2002. 2) 
    • Development of 3D stackable PRAM (Phase-change Random Access Memory) with 19nm technology as a Project Leader who supervises a Technology Development (TD) department and characterization of tens of Gbit-level PRAM prototype device.
    • Development and production of 512Mb, 1Gb PRAM with 39/58/82nm technologies as a Part Leader who led and co-worked with a dozen of device engineers for improving cell performances and reliabilities of wafer-/package-level PRAM device.

Awards

  • Future Creators Prize in 2020 from Samsung Semiconductor Division for contributing "The Full Integration of 3D Stackable Non-volatile Memory Device with 19.5nm Technology Node"


  • Best Paper Prize in 2014 from 21st Korean Conferences of Semiconductors for contributing "The Emulation of Neuron Spiking and Synaptic Plasticity in Phase Change Memory (PCM) for Neuromorphic Applications"

Education

  • Seoul National University: Ph.D. in Materials Science and Engineering (1993.3~1997.8) 
  • Seoul National University: M.S. in Metallurgical Engineering (1991.3~1993.2)
  • Pohang University of Science and Technology: B.S. in Materials Science and Engineering (1987.3~1991.2)

Address

Dep. of Semiconductor Engineering, POSTECH 77,

Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea

(37673)


TEL: +82-54-279-7085

E-mail: daehwankang@postech.ac.kr


Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL)

All rights reserved | Designed by greypixel

Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL) All rights reserved | Designed by greypixel