Address
Dep. of Semiconductor Engineering, POSTECH 77,
Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea
(37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
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Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL)
All rights reserved | Designed by greypixel
Address
Dep. of Semiconductor Engineering, POSTECH 77, Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea (37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL) All rights reserved | Designed by greypixel
J Jeong, J Lee, G Koh, D Kang Memory cell and memory device comprising selection device layer, middle electrode layer and variable resistance layer - US Patent 10,566,529, 2020