J Jeong, D Kang, D Kim, K Lee Memory devices having cross point memory arrays therein with multi-level word line and bit line structures - US Patent 10,644,069, 2020
SIM Kyu-Rie, G Koh, D Kang Memory device and electronic apparatus including the same - US Patent 10,734,450, 2020
LEE Kwang-Woo, D Kang, G Koh Semiconductor devices and methods of manufacturing the same - US Patent 10,615,341, 2020
M Terai, D Kang, G Koh Variable resistance memory devices and methods of manufacturing the same - US Patent 10,546,999, 2020
I Park, G Koh, D Kang Memory device and method of manufacturing the same - US Patent 10,580,979, 2020
J Jeong, J Lee, G Koh, D Kang Memory cell and memory device comprising selection device layer, middle electrode layer and variable resistance layer - US Patent 10,566,529, 2020
SIM Kyu-Rie, D Kang, G Koh Variable resistance memory devices and methods of manufacturing the same - US Patent 10,593,874, 2020
Address
Dep. of Semiconductor Engineering, POSTECH 77,
Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea
(37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
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Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL)
All rights reserved | Designed by greypixel
Address
Dep. of Semiconductor Engineering, POSTECH 77, Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea (37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL) All rights reserved | Designed by greypixel
