Address
Dep. of Semiconductor Engineering, POSTECH 77,
Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea
(37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
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Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL)
All rights reserved | Designed by greypixel
Address
Dep. of Semiconductor Engineering, POSTECH 77, Cheongam-ro, Nam-Gu, Pohang, Gyeongbuk-Do, Korea (37673)
TEL: +82-54-279-7085
E-mail: daehwankang@postech.ac.kr
Copyright ⓒ 2023. Chalcogenide Semiconductor Lab (CSL) All rights reserved | Designed by greypixel
Chang-Wook Jeong, Hyeong-Jun Kim, Dae-Hwan Kang, Seung-Pil Ko, Dong-Won Lim, “Multi-level cell phase change memory devices having controlled resistance-drift parameter, memory systems employing such devices and methods of reading memory devices” UP079,886 Samsung Electronics Co. Ltd. 2008 (US 07701749) 2010.04.20.